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1996 data sheet description the m pd78p058f is an electro magnetic interference (emi) noise reduction version of the m pd78p058. the m pd78p058f is a member of the m pd78058f subseries of the 78k/0 series, in which the on-chip mask rom of the m pd78058f is replaced with one-time programmable (otp) rom. because this device can be programmed by users, it is suited for applications involving the small-scale production of many different products, and for rapid development and time-to-market of new products. details are given in the following users manuals. be sure to read them before starting design. m pd78058f, 78058fy subseries users manual : u12068e 78k/0 series users manual instructions : u12326e features ? emi noise reduction version (overall peak level reduced by 5 to 10 db) ? pin compatible with mask rom versions (except the v pp pin) ? internal prom : 60 kbytes note 1 programmable once only (ideal for small-scale production) ? internal high-speed ram : 1024 bytes ? internal expansion ram : 1024 bytes note 2 ? buffer ram : 32 bytes ? operable in the same supply voltage range as mask rom versions (v dd = 2.7 to 6.0 v) ? one of the qtop tm microcontrollers notes 1. the internal prom capacity can be changed with the memory size switching register (ims). 2. the internal expansion ram capacity can be changed with the internal expansion ram size switching register (ixs). remarks 1. for the difference between prom and mask rom versions, see 1. differences between m pd78p058f and mask rom versions . 2. qtop microcontroller is the general name of the microcontrollers with on-chip one-time prom that are totally supported by the nec writing service (from writing to marking, screening and testing). m pd78p058f mos integrated circuit the information in this document is subject to change without notice. the mark shows major revised points. 8-bit single-chip microcontroller document no. u11796ej2v0ds00 (2nd edition) date published september 1997 n printed in japan
2 m pd78p058f ordering information part number package internal rom m pd78p058fgc-3b9 80-pin plastic qfp (14 14 mm, resin thickness: 2.7 mm) one-time prom m pd78p058fgc-8bt 80-pin plastic qfp (14 14 mm, resin thickness: 1.4 mm) one-time prom caution the m pd78p058fgc contains two types of packages (see 8. package drawings). for the packages which can be supplied, consult your local nec sales representative.
3 m pd78p058f 78k/0 series product development these products are a further development in the 78k/0 series. the designations appearing inside the boxes are subseries names. note under planning pd78014 pd78002 pd78083 pd78002y 100-pin 100-pin 100-pin 64-pin 64-pin 64-pin 42/44-pin control y subseries products are compatible with i 2 c bus. a timer was added to the pd78054, and the external interface function was enhanced. emi noise reduction version of the pd78078. rom-less versions of the pd78078. an a/d converter and 16-bit timer were added to the pd78002. an a/d converter was added to the pd78002. basic subseries for control. on-chip uart, capable of operating at a low voltage (1.8 v). pd780018ay 100-pin serial i/o of the pd78078y was enhanced, and only selected functions are provided. pd78078 pd78070a pd78075b pd78070ay m m mm m mm m mm m m m m m m inverter control pd780964 64-pin m an a/d converter of the pd780924 was enhanced. pd780988 64-pin m an inverter control, timer, and sio of the pd780964 were enhanced, and rom and ram were expanded. pd78078y m m pd78075by pd78018f pd780001 pd78018fy pd78014y 80-pin 80-pin 64-pin 78k/0 series products in mass production products under development emi noise reduction version of the pd78054. uart and d/a converter were added to the pd78014, and i/o was enhanced. low-voltage (1.8 v) operation versions of the pd78014 with several rom and ram capacities available. an a/d converter of the pd780024 was enhanced. emi noise reduction version of the pd78018f. on-chip inverter control circuit and uart, emi noise reduction version. serial i/o of the pd78018f was enhanced, emi noise reduction version. serial i/o of the pd78054 was enhanced, emi noise reduction version. pd780058 80-pin m mm pd780034 pd780024 pd78014h pd780034y pd780024y 64-pin 64-pin 64-pin mm mm m m m m m m m m m m fip tm drive pd78044f 100-pin 80-pin 80-pin m m the i/o and fip c/d of the pd78044f were enhanced, display output total: 53 the i/o and fip c/d of the pd78044h were enhanced, display output total: 48 n-ch open-drain input/output was added to the pd78044f, display output total: 34 basic subseries for driving fip, display output total: 34 m m 100-pin pd780924 64-pin m pd780308 pd78064b pd78064 100-pin 100-pin 100-pin m m sio of the pd78064 was enhanced, and rom and ram were expanded. emi noise reduction version of the pd78064. basic subseries for driving lcds, on-chip uart. m pd780308y m pd78064y m lcd drive m m lv pd78p0914 64-pin m on-chip pwm output, lv digital code decoder, hsync counter. pd78054 m pd78054y m pd78058fy m pd780058y note m pd78058f m pd78044h m m pd780228 pd780208 m m m iebus tm supported pd78098b 80-pin m emi noise reduction version of the pd78098. the iebus controller was added to the pd78054. pd78098 80-pin m m meter control pd780973 80-pin m on-chip automobile meter driving controller/driver.
4 m pd78p058f function rom timer 8-bit 10-bit 8-bit v dd external serial interface i/o min. subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control m pd78075b 32 k to 40 k 4ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 88 1.8 v available m pd78078 48 k to 60 k m pd78070a C 61 2.7 v m pd780058 24 k to 60 k 2ch 3ch (time-division uart: 68 1.8 v 1ch) m pd78058f 48 k to 60 k 3ch (uart: 1ch) 69 2.7 v m pd78054 16 k to 60 k 2.0 v m pd780034 8 k to 32 k C 8ch C 3ch (uart: 1ch, 51 1.8 v m pd780024 8ch C time-division 3-wire: 1ch) m pd78014h 2ch 53 m pd78018f 8 k to 60 k m pd78014 8 k to 32 k 2.7 v m pd780001 8 k C C 1ch 39 C m pd78002 8 k to 16 k 1ch C 53 available m pd78083 C 8ch 1ch (uart: 1ch) 33 1.8 v C inverter m pd780988 32 k to 60 k 3ch note 1 C 1ch C 8ch C 3ch (uart: 2ch) 47 4.0 v available control m pd780964 8 k to 32 k note 2 2ch (uart: 2ch) 2.7 v m pd780924 8ch C fip m pd780208 32 k to 60 k 2ch 1ch 1ch 1ch 8ch C C 2ch 74 2.7 v C drive m pd780228 48 k to 60 k 3ch C C 1ch 72 4.5 v m pd78044h 32 k to 48 k 2ch 1ch 1ch 68 2.7 v m pd78044f 16 k to 40 k 2ch lcd m pd780308 48 k to 60 k 2ch 1ch 1ch 1ch 8ch C C 3ch (time-division uart: 57 2.0 v C drive 1ch) m pd78064b 32 k 2ch (uart: 1ch) m pd78064 16 k to 32 k iebus m pd78098b 40 k to 60 k 2ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 69 2.7 v available supported m pd78098 32 k to 60 k meter m pd780973 24 k to 32 k 3ch 1ch 1ch 1ch 5ch C C 2ch (uart: 1ch) 56 4.5 v C control lv m pd78p0914 32 k 6ch C C 1ch 8ch C C 2ch 54 4.5 v available the major functional differences among the subseries are shown below. notes 1. 16-bit timer : 2 channels 10-bit timer : 1 channel 2. 10-bit timer : 1 channel
5 m pd78p058f function description item function internal memory ? prom : 60 kbytes note 1 ? ram high-speed ram : 1024 bytes expansion ram : 1024 bytes note 2 buffer ram : 32 bytes memory space 64 kbytes general register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time minimum instruction execution time is variable. when main system 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (@ 5.0-mhz operation) clock is selected when subsystem 122 m s (@ 32.768-khz operation) clock is selected instruction set ? 16-bit operation ? multiply/divide (8-bit 8-bit, 16-bit ? 8-bit) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjust, etc. i/o port total : 69 ? cmos input : 2 ? cmos input/output : 63 ? n-ch open-drain input/output : 4 a/d converter 8-bit resolution 8 ch d/a converter 8-bit resolution 2 ch serial interface ? 3-wire serial i/o, sbi, or 2-wire serial i/o mode selectable : 1 ch ? 3-wire serial i/o mode (with on-chip max. 32-byte automatic transmit/receive function) : 1 ch ? 3-wire serial i/o or uart mode selectable : 1 ch timer ? 16-bit timer/event counter : 1 ch ? 8-bit timer/event counter : 2 ch ? watch timer : 1 ch ? watchdog timer : 1 ch timer output 3 pins (14-bit pwm output: 1 pin) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, and 5.0 mhz (@ 5.0-mhz operation with main system clock) 32.768 khz (@ 32.768-khz operation with subsystem clock) buzzer output 1.2 khz, 2.4 khz, 4.9 khz and 9.8 khz (@ 5.0-mhz operation with main system clock) vectored maskable internal: 13, external: 7 interrupt non-maskable internal: 1 source software 1 test input internal: 1, external: 1 supply voltage v dd = 2.7 to 6.0 v operating ambient temperature t a = C40 to +85 c package ? 80-pin plastic qfp (14 14 mm, resin thickness: 2.7 mm) ? 80-pin plastic qfp (14 14 mm, resin thickness: 1.4 mm) notes 1. the internal prom capacity can be changed with the memory size switching register (ims). 2. the internal expansion ram capacity can be changed with the internal expansion ram size switching register (ixs).
6 m pd78p058f pin configurations (top view) (1) normal operating mode 80-pin plastic qfp (14 14 mm, resin thickness: 2.7 mm) m pd78p058fgc-3b9 80-pin plastic qfp (14 14 mm, resin thickness: 1.4 mm) m pd78p058fgc-8bt cautions 1. connect the v pp pin to v ss . 2. the av dd pin functions as both an a/d converter power supply and a port power supply. when the m pd78p058f is used in applications where the noise generated inside the microcontroller needs to be reduced, connect the av dd pin to another power supply which has the same potential as v dd . 3. the av ss pin functions as both grounds of an a/d converter and d/a converter and of a port. when the m pd78p058f is used in applications where the noise generated inside the microcontroller needs to be reduced, connect the av ss pin to a ground line other than v ss . 1 p15/ani5 21 40 80 61 60 p14/ani4 p00/intp0/ti00 p42/ad2 41 reset 20 p64/rd p65/wr 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 p127/rtp7 p126/rtp6 p125/rtp5 p124/rtp4 p123/rtp3 p122/rtp2 p121/rtp1 p120/rtp0 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/r x d p71/so2/t x d p72/sck2/asck p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0 p26/so0/sb1 p27/sck0 p40/ad0 p41/ad1 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd xt1/p07 xt2 v pp x1 x2 v dd p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01
7 m pd78p058f a8 to a15 : address bus pcl : programmable clock ad0 to ad7 : address/data bus rd : read strobe ani0 to ani7 : analog input reset : reset ano0, ano1 : analog output rtp0 to rtp7 : real-time output port asck : asynchronous serial clock r x d : receive data astb : address strobe sb0, sb1 : serial bus av dd : analog power supply sck0 to sck2 : serial clock av ref0 , av ref1 : analog reference voltage si0 to si2 : serial input av ss : analog ground so0 to so2 : serial output busy : busy stb : strobe buz : buzzer clock ti00, ti01 : timer input intp0 to intp6 : interrupt from peripherals ti1,ti2 : timer input p00 to p07 : port 0 to0 to to2 : timer output p10 to p17 : port 1 t x d : transmit data p20 to p27 : port 2 v dd : power supply p30 to p37 : port 3 v pp : programming power supply p40 to p47 : port 4 v ss : ground p50 to p57 : port 5 wait : wait p60 to p67 : port 6 wr : write strobe p70 to p72 : port 7 x1, x2 : crystal (main system clock) p120 to p127 : port 12 xt1, xt2 : crystal (subsystem clock) p130, p131 : port 13
8 m pd78p058f (2) prom programming mode 80-pin plastic qfp (14 14 mm, resin thickness: 2.7 mm) m pd78p058fgc-3b9 80-pin plastic qfp (14 14 mm, resin thickness: 1.4 mm) m pd78p058fgc-8bt cautions 1. (l) : individually connect to v ss via a pull-down resistor. 2. v ss : connect to gnd. 3. reset : set to low level. 4. open : no connection a0 to a16 : address bus reset : reset ce : chip enable v dd : power supply d0 to d7 : data bus v pp : programming power supply oe : output enable v ss : ground pgm : program 1 21 40 80 61 60 a9 a2 41 20 oe ce d0 d1 d2 d3 d4 d5 d6 d7 reset 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 (l) v ss (l) v dd (l) a0 a1 a3 a4 a5 a6 a7 a8 a16 a10 a11 a12 a13 v ss a14 a15 (l) (l) (l) (l) pgm (l) open (l) v pp open (l) v dd v dd v ss (l)
9 m pd78p058f block diagram to0/p30 16-bit timer/ event counter ti00/intp0/p00 ti01/intp1/p01 to1/p31 8-bit timer/ event counter 1 ti1/p33 to2/p32 8-bit timer/ event counter 2 ti2/p34 watchdog timer watch timer si0/sb0/p25 serial interface 0 so0/sb1/p26 sck0/p27 si1/p20 serial interface 1 so1/p21 sck1/p22 a/d converter av ref0 ani0/p10 to ani7/p17 interrupt control intp0/p00 to intp6/p06 buzzer output buz/p36 clock output control pcl/p35 p00 port0 p01 to p06 p07 port1 p10 to p17 port12 p120 to p127 port2 p20 to p27 port3 p30 to p37 port4 p40 to p47 port5 p50 to p57 port6 p60 to p67 port7 p70 to p72 external access ad0/p40 to reset x1 x2 xt1/p07 xt2 78k/0 cpu core prom 60 k bytes ram 2080 bytes system control v dd v ss av dd av ss v pp si2/rxd/p70 serial interface 2 so2/txd/p71 sck2/asck/p72 stb/p23 busy/p24 d/a converter ano0/p130, ano1/p131 av ref1 ad7/p47 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 port13 real-time output port p130, p131 rtp0/p120 to rtp7/p127
10 m pd78p058f contents 1. differences between m pd78p058f and mask rom versions ..................................... 11 2. pin functions ............................................................................................................................... .12 2.1 pins in normal operating mode ............................................................................................................ 12 2.2 pins in prom programming mode ....................................................................................................... 16 2.3 pin input/output circuits and recommended connection of unused pins .................................. 17 3. memory size switching register (ims) ............................................................................... 21 4. internal expansion ram size switching register (ixs) ............................................. 22 5. prom programming .................................................................................................................... 23 5.1 operating modes ............................................................................................................................... ...... 23 5.2 prom write procedure .......................................................................................................................... 25 5.3 prom read procedure .......................................................................................................................... 29 6. screening of one-time prom versions ............................................................................. 30 7. electrical specifications ..................................................................................................... 31 8. package drawings ..................................................................................................................... 63 9. recommended soldering conditions ................................................................................ 65 appendix a. development tools ................................................................................................. 67 appendix b. related documents ................................................................................................ 71
11 m pd78p058f 1. differences between m pd78p058f and mask rom versions the m pd78p058f is a single-chip microcontroller with an on-chip one-time prom. setting the memory size switching register (ims) and internal expansion ram size switching register (ixs) enables identical functions to mask rom versions ( m pd78056f and 78058f) except the functions of prom specifications and of mask options for p60 to p63. differences between the m pd78p058f and mask rom versions are shown in table 1-1. table 1-1. differences between m pd78p058f and mask rom versions item m pd78p058f mask rom versions internal rom structure one-time prom mask rom internal rom capacity 60 kbytes m pd78056f : 48 kbytes m pd78058f : 60 kbytes internal expansion ram capacity 1024 bytes m pd78056f : none m pd78058f : 1024 bytes change of internal rom capacity by can be changed note cannot be changed memory size switching register (ims) change of internal expansion ram can be changed note cannot be changed capacity by internal expansion ram size switching register (ixs) ic pin none provided v pp pin provided none pull-up resistor on-chip mask option none provided of p60 to p63 pins electrical specifications, see each data sheet. recommended soldering conditions note the reset input sets the internal prom capacity and internal expansion ram capacity to 60 kbytes and 1024 bytes, respectively. caution the prom version and mask rom version differ in noise tolerance and noise emission. when replacing a prom version with a mask rom version when switching from experimental production to mass production, make a thorough evaluation with a cs version (not es version) of the mask rom version.
12 m pd78p058f 2. pin functions 2.1 pins in normal operating mode (1) port pins (1/2) pin name input/output function after reset alternate function p00 input port 0 input only input intp0/ti00 8-bit input/output p01 input/output port input/output is specifiable input intp1/ti01 bit-wise. when used as the p02 input port, it is possible to intp2 use an on-chip pull-up p03 resistor by software. intp3 p04 intp4 p05 intp5 p06 intp6 p07 note 1 input input only input xt1 p10 to p17 input/output port 1 input ani0 to ani7 8-bit input/output port input/output is specifiable bit-wise. when used as the input port, it is possible to use an on-chip pull-up resistor by software. note 2 p20 input/output port 2 input si1 8-bit input/output port p21 input/output is specifiable bit-wise. so1 when used as the input port, it is possible to p22 use an on-chip pull-up resistor by software. sck1 p23 stb p24 busy p25 si0/sb0 p26 so0/sb1 p27 sck0 p30 input/output port 3 input to0 8-bit input/output port p31 input/output is specifiable bit-wise. to1 when used as the input port, it is possible to p32 use an on-chip pull-up resistor by software. to2 p33 ti1 p34 ti2 p35 pcl p36 buz p37 notes 1. when the p07/xt1 pins are used as the input ports, set the processor clock control register (pcc) bit 6 (frc) to 1, and be sure not to use the feedback resistor of the subsystem clock oscillation circuit. 2. when the p10/ani0 to p17/ani7 pins are used as the analog inputs for a/d converter, set port 1 to input mode. the on-chip pull-up resistors are automatically disabled. caution for pins which also function as port pins, do not perform the following operations during a/d conversion. if these operations are performed, the total error ratings cannot be kept. <1> rewrite the output latch while the pin is used as a port pin. <2> change the output level of the pin used as an output pin, even if it is not used as a port pin.
13 m pd78p058f (1) port pins (2/2) pin name input/output function after reset alternate function p40 to p47 input/output port 4 input ad0 to ad7 8-bit input/output port input/output is specifiable as 8-bit unit. when used as the input port, it is possible to use an on-chip pull-up resistor by software. set test input flag (krif) to 1 by falling edge detection. p50 to p57 input/output port 5 input a8 to a15 8-bit input/output port it is possible to directly drive leds. input/output is specifiable bit-wise. when used as the input port, it is possible to use an on-chip pull-up resistor by software. p60 input/output port 6 n-ch open-drain input 8-bit input/output port input/output port. p61 input/output is it is possible to directly specifiable bit-wise. drive leds. p62 p63 p64 when used as the input input rd port, it is possible to p65 use an on-chip pull-up wr resistor by software. p66 wait p67 astb p70 input/output port 7 input si2/r x d 3-bit input/output port p71 input/output is specifiable bit-wise. so2/t x d when used as the input port, it is possible to p72 use an on-chip pull-up resistor by software. sck2/asck p120 to p127 input/output port 12 input rtp0 to rtp7 8-bit input/output port input/output is specifiable bit-wise. when used as the input port, it is possible to use an on-chip pull-up resistor by software. p130, p131 input/output port 13 input ano0, ano1 2-bit input/output port input/output is specifiable bit-wise. when used as the input port, it is possible to use an on-chip pull-up resistor by software. caution for pins which also function as port pins, do not perform the following operations during a/d conversion. if these operations are performed, the total error ratings cannot be kept. <1> rewrite the output latch while the pin is used as a port pin. <2> change the output level of the pin used as an output pin, even if it is not used as a port pin.
14 m pd78p058f (2) non-port pins (1/2) pin name input/output function after reset alternate function intp0 input external interrupt request inputs, with specifiable input p00/ti00 valid edges (rising edge, falling edge, and both intp1 rising and falling edges) p01/ti01 intp2 p02 intp3 p03 intp4 p04 intp5 p05 intp6 p06 si0 input serial data input of the serial interface input p25/sb0 si1 p20 si2 p70/r x d so0 output serial data output of the serial interface input p26/sb1 so1 p21 so2 p71/t x d sb0 input/output serial data input/output of the serial interface input p25/si0 sb1 p26/so0 sck0 input/output serial clock input/output of the serial interface input p27 sck1 p22 sck2 p72/asck stb output automatic transmitting/receiving strobe output of input p23 the serial interface busy input automatic transmitting/receiving busy input of the input p24 serial interface r x d input serial data input for asynchronous serial interface input p70/si2 t x d output serial data output for asynchronous serial interface input p71/so2 asck input serial clock input for asynchronous serial interface input p72/sck2 ti00 input external count clock input to 16-bit timer (tm0) input p00/intp0 ti01 capture trigger signal input to capture register p01/intp1 (cr00) ti1 external count clock input to 8-bit timer (tm1) p33 ti2 external count clock input to 8-bit timer (tm2) p34 to0 output 16-bit timer (tm0) output input p30 (can be used together with 14-bit pwm output.) to1 8-bit timer (tm1) output p31 to2 8-bit timer (tm2) output p32
15 m pd78p058f (2) non-port pins (2/2) pin name input/output function after reset alternate function pcl output clock output (for trimming main system clock and input p35 subsystem clock) buz output buzzer output input p36 rtp0 to rtp7 output real-time output port which outputs data in syn- input p120 to p127 chronization with trigger ad0 to ad7 input/output low-order address/data bus when expanding input p40 to p47 memory externally a8 to a15 output high-order address bus when expanding memory input p50 to p57 externally rd output strobe signal output for the external memory read input p64 operation wr strobe signal output for the external memory write input p65 operation wait input wait insertion when accessing external memory input p66 astb output strobe output to externally latches address infor- input p67 mation which is output to ports 4 and 5 for accessing external memory ani0 to ani7 input analog input of a/d converter input p10 to p17 ano0, ano1 output analog output of d/a converter input p130, p131 av ref0 input reference voltage input of a/d converter av ref1 input reference voltage input of d/a converter av dd analog power supply of a/d converter (shared with the port power supply) av ss ground potential of a/d converter and d/a converter (shared with the port ground potential) reset input system reset input x1 input main system clock oscillation crystal connection x2 xt1 input subsystem clock oscillation crystal connection input p07 xt2 v dd positive power supply (except for port) v pp high-voltage applied during program write/verify. connected to v ss in normal operating mode. v ss ground potential (except for port) cautions 1. the av dd pin functions as both an a/d converter power supply and a port power supply. when the m pd78p058f is used in applications where the noise generated inside the microcontroller needs to be reduced, connect the av dd pin to another power supply which has the same potential as v dd . 2. the av ss pin functions as both grounds of an a/d converter and d/a converter and of a port. when the m pd78p058f is used in applications where the noise generated inside the microcontroller needs to be reduced, connect the av ss pin to a ground line other than v ss .
16 m pd78p058f 2.2 pins in prom programming mode pin name input/output function reset input prom programming mode setting when +5 v or +12.5 v is applied to the v pp pin and a low-level signal is applied to the reset pin, this chip is set in the prom programming mode. v pp input prom programming mode setting and high-voltage applied during program write/ verification a0 to a16 input address bus d0 to d7 input/output data bus ce input prom enable input/program pulse input oe input read strobe input to prom pgm input program/program inhibit input in prom programming mode v dd positive power supply v ss ground potential
17 m pd78p058f 2.3 pin input/output circuits and recommended connection of unused pins types of input/output circuits of the pins and recommended connection of unused pins are shown in table 2-1. for the configuration of each type of input/output circuit, see figure 2-1. table 2-1. pin input/output circuit type (1/2) pin name input/output input/output recommended connection when unused circuit type p00/intp0/ti00 2 input connect to v ss . p01/intp1/ti01 8-d input/output independently connect to v ss through resistor. p02/intp2 p03/intp3 p04/intp4 p05/intp5 p06/intp6 p07/xt1 16 input connect to v dd . p10/ani0 to p17/ani7 11-c input/output independently connect to v dd or v ss through resistor. p20/si1 8-d p21/so1 5-j p22/sck1 8-d p23/stb 5-j p24/busy 8-d p25/si0/sb0 10-c p26/so0/sb1 p27/sck0 p30/to0 5-j p31/to1 p32/to2 p33/ti1 8-d p34/ti2 p35/pcl 5-j p36/buz p37 p40/ad0 to p47/ad7 5-o independently connect to v dd through resistor.
18 m pd78p058f table 2-1. pin input/output circuit type (2/2) pin name input/output input/output recommended connection when unused circuit type p50/a8 to p57/a15 5-j input/output independently connect to v dd or v ss through resistor. p60 to p63 13-h independently connect to v dd through resistor. p64/rd 5-j independently connect to v dd or v ss through resistor. p65/wr p66/wait p67/astb p70/si2/rxd 8-d p71/so2/txd 5-j p72/sck2/asck 8-d p120/rtp0 to p127/rtp7 5-j p130/ano0, p131/ano1 12-b independently connect to v ss through resistor. reset 2 input xt2 16 leave open. av ref0 connect to v ss . av ref1 connect to v dd . av dd connect to another power supply which has the same potential as v dd . av ss connect to another ground line which has the same potential as v ss . v pp connect to v ss .
19 m pd78p058f figure 2-1. pin input/output circuits (1/2) schmitt-triggered input with hysteresis characteristic type 10-c type 8-d type 2 type 5-j in type 11-c type 5-o pullup enable data output disable av dd av ss p-ch n-ch p-ch in/out av dd pullup enable data output disable av dd av ss p-ch n-ch p-ch in/out av dd input enable pullup enable p-ch av dd data output disable n-ch in/out av dd av ss p-ch open drain pullup enable data av dd av ss p-ch n-ch p-ch in/out av dd output disable enable av dd av ss pullup enable data output disable in/out v ref input (threshold voltage) av dd av ss n-ch p-ch + - comparator n-ch p-ch p-ch
20 m pd78p058f figure 2-1. pin input/output circuits (2/2) type 12-b type 16 type 13-h pullup enable data output disable input enable p-ch in/out av dd av dd av ss av ss p-ch n-ch n-ch p-ch analog output voltage feedback cut-off p-ch xt2 xt1 data output disable in/out n-ch middle-high voltage input buffer p-ch av dd av ss rd
21 m pd78p058f 3. memory size switching register (ims) this is a register to disable use of part of internal memories by software. by setting this memory size switching register (ims), it is possible to get the same memory mapping as that of a mask rom version having different internal memories (rom). the ims register is set with an 8-bit memory manipulation instruction. reset input sets ims to cfh. figure 3-1. memory size switching register format selection of internal ram2 ram1 ram0 high-speed ram capacity 1 1 0 1024 bytes others setting prohibited selection of internal rom3 rom2 rom1 rom0 rom capacity 1 1 0 0 48 kbytes 1 1 1 0 56 kbytes note 1 1 1 1 60 kbytes others setting prohibited 7654321 0 symbol ims address r/w fff0h cfh r/w after reset ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 note set the internal rom capacity to 56 kbytes or less when external device expansion function is used. table 3-1 shows the setting values of ims which make the memory mapping the same as that of the mask rom versions. table 3-1. memory size switching register setting values target mask rom version ims setting value m pd78056f cch m pd78058f cfh
22 m pd78p058f 4. internal expansion ram size switching register (ixs) this is a register to set the internal expansion ram capacity by software. by setting this internal expansion ram size switching register (ixs), it is possible to get the same memory mapping as that of a mask rom version having different internal expansion ram. the ixs register is set with an 8-bit memory manipulation instruction. reset input sets ixs to 0ah. figure 4-1. internal expansion ram size switching register format 0 0 0 0 ixram3 ixram2 ixram1 ixram0 7654321 0 symbol ixs address r/w fff4h 0ah after reset w table 4-1 shows the setting values of ixs which make the memory mapping the same as that of the mask rom versions. table 4-1. internal expansion ram size switching register setting values target mask rom version ixs setting value m pd78056f 0ch m pd78058f 0ah remark even if a m pd78p058f program that includes "mov ixs, #0ch" is implemented on the m pd78056f, its operation will not be affected. selection of internal ixram3 ixram2 ixram1 ixram0 expansion ram capacity 1 1 0 0 0 byte 1 0 1 0 1024 bytes others setting prohibited
m pd78p058f 23 5. prom programming the m pd78p058f has an on-chip 60-kbyte prom as a program memory. for programming, set the prom programming mode by the v pp and reset pins. for connecting unused pins, refer to pin configurations (top view) (2) prom programming mode . caution program writing should be performed in the address range 0000h to efffh (the last address, efffh, should be specified). writing cannot be performed with a prom programmer that cannot specify the write addresses. 5.1 operating modes when +5 v or +12.5 v is applied to the v pp pin and a low level signal is applied to the reset pin, the prom programming mode is set. this mode will become the operating mode as shown in table 5-1 when the ce, oe and pgm pins are set as shown. further, when the read mode is set, it is possible to read the contents of the prom. table 5-1. operating modes of prom programming pin reset v pp v dd ce oe pgm d0 to d7 operating mode page data latch l +12.5 v +6.5 v h l h data input page write h h l high-impedance byte write l h l data input program verify l l h data output program inhibit h h high-impedance ll read +5 v +5 v l l h data output output disable l h high-impedance standby h high-impedance remark : l or h
m pd78p058f 24 (1) read mode read mode is set if ce = l, oe = l are set. (2) output disable mode data output becomes high-impedance, and is in the output disable mode, if oe = h is set. therefore, it allows data to be read from any device by controlling the oe pin, if multiple m pd78p058fs are connected to the data bus. (3) standby mode standby mode is set if ce = h is set. in this mode, data outputs become high-impedance irrespective of the oe status. (4) page data latch mode page data latch mode is set if ce = h, pgm = h, oe = l are set at the beginning of page write mode. in this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) page write mode after 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the pgm pin with ce = h, oe = h. then, program verification can be performed, if ce = l, oe = l are set. if programming is not performed by a one-time program pulse, x (x 10) write and verification operations should be executed repeatedly. (6) byte write mode byte write is executed when a 0.1-ms program pulse (active low) is applied to the pgm pin with ce = l, oe = h. then, program verification can be performed if oe = l is set. if programming is not performed by a one-time program pulse, x (x 10) write and verification operations should be executed repeatedly. (7) program verify mode program verify mode is set if ce = l, pgm = h, oe = l are set. in this mode, check if a write operation is performed correctly after the write. (8) program inhibit mode program inhibit mode is used when the oe pin, v pp pin, and d0 to d7 pins of multiple m pd78p058fs are connected in parallel and a write is performed to one of those devices. when a write operation is performed, the page write mode or byte write mode described above is used. at this time, a write is not performed to a device which has the pgm pin driven high.
m pd78p058f 25 5.2 prom write procedure figure 5-1. page program mode flowchart remark g = start address n = program last address start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x + 1 x = 10? address = n? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 0.1-ms program pulse verify 4 bytes verify all bytes end of writing defective product
m pd78p058f 26 figure 5-2. page program mode timing a2 to a16 a0, a1 d0 to d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il page data latch page program program verify data output data input
m pd78p058f 27 figure 5-3. byte program mode flowchart remark g = start address n = program last address start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 x = x + 1 address = n? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 x = 10? 0.1-ms program pulse verify verify all bytes end of writing defective product
m pd78p058f 28 figure 5-4. byte program mode timing cautions 1. v dd should be applied before v pp , and removed after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. reliability may be adversely affected if removal/reinsertion is performed while +12.5 v is being applied to v pp . a0 to a16 d0 to d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il data output data input program program verify
m pd78p058f 29 5.3 prom read procedure the contents of prom are readable to the external data bus (d0 to d7) according to the read procedure shown below. (1) fix the reset pin at low level, supply +5 v to the v pp pin, and connect all other unused pins as shown in pin configurations (top view) (2) prom programming mode . (2) supply +5 v to the v dd and v pp pins. (3) input address of read data into the a0 to a16 pins. (4) read mode (5) output data to d0 to d7 pins. the timings of the above steps (2) to (5) are shown in figure 5-5. figure 5-5. prom read timings a0 to a16 d0 to d7 ce (input) oe (input) hi-z hi-z data output address input
m pd78p058f 30 6. screening of one-time prom versions the one-time prom version ( m pd78p058fgc-3b9, 78p058fgc-8bt) cannot be tested completely by nec before it is shipped, because of its structure. it is recommended to perform screening to verify prom after writing necessary data and performing high-temperature storage under the conditions below. storage temperature storage time 125 c 24 hours nec offers for a fee one-time prom writing, marking, screening and verify services for products designated as "qtop microcontrollers". for details, contact an nec sales representative.
m pd78p058f 31 7. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions rating unit supply voltage v dd C0.3 to +7.0 v v pp C0.3 to +13.5 v av dd C0.3 to v dd + 0.3 v av ref0 C0.3 to v dd + 0.3 v av ref1 C0.3 to v dd + 0.3 v av ss C0.3 to +0.3 v input voltage v i1 p00 to p07, p10 to p17, p20 to p27, C0.3 to v dd + 0.3 v p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, x1, x2, xt2, reset v i2 p60 to p63 n-ch open-drain C0.3 to +16 v v i3 a9 prom programming mode C0.3 to +13.5 v output voltage v o C0.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pins av ss C 0.3 to av ref0 + 0.3 v output current, high i oh per pin C10 ma total for p01 to p06, p30 to p37, p56, p57, C15 ma p60 to p67, p120 to p127 total for p10 to p17, p20 to p27, p40 to p47, C15 ma p50 to p55, p70 to p72, p130, p131 output current, low i ol note per pin peak value 30 ma r.m.s. value 15 ma total for p50 to p55 peak value 100 ma r.m.s. value 70 ma total for p56, p57, p60 to p63 peak value 100 ma r.m.s. value 70 ma total for p10 to p17, p20 to p27, p40 to p47, p70 to p72, p130, p131 total for p01 to p06, p30 to p37, p64 to p67, p120 to p127 operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c note r.m.s. values should be calculated as follows: [r.m.s. value] = [peak value] x ? duty caution product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, even momentarily. in other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, alternate-function pin characteristics are the same as port pin characteristics. peak value 50 ma r.m.s. value 20 ma peak value 50 ma r.m.s. value 20 ma
m pd78p058f 32 main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) resonator recommended parameter test conditions min. typ. max. unit circuit ceramic resonator oscillation frequency v dd = oscillation voltage range 1.0 5.0 mhz (f x ) note 1 oscillation stabilization after v dd has reached min. of 4 ms time note 2 oscillation voltage range crystal resonator oscillation frequency 1.0 5.0 mhz (f x ) note 1 oscillation stabilization v dd = 4.5 to 6.0 v 10 ms time note 2 30 external clock x1 input frequency 1.0 5.0 mhz (f x ) note 1 x1 input high-/low-level 85 500 ns width (t xh /t xl ) notes 1. only the oscillator characteristics are shown. see the ac characteristics for instruction execution times. 2. this is the time required for oscillation to stabilize after a reset or stop mode release. cautions 1. when the main system clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by broken lines to prevent the influence of wiring capacitance, etc. ? the wiring should be kept as short as possible. ? no other signal lines should be crossed. ? keep away from lines carrying a high fluctuating current. ? the oscillator capacitor grounding point should always be at the same potential as v ss . ? do not connect to a ground pattern carrying a high current. ? a signal should not be taken from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. x1 v pp x2 c2 c1 x1 v pp x2 c2 c1 x2 x1 pd74hcu04 m
m pd78p058f 33 subsystem clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) resonator recommended parameter test conditions min. typ. max. unit circuit crystal resonator oscillation frequency 32 32.768 35 khz (f xt ) note 1 oscillation stabilization v dd = 4.5 to 6.0 v 1.2 2 s time note 2 10 external clock xt1 input frequency 32 100 khz (f xt ) note 1 xt1 input 5 15 m s high-/low-level width (t xth /t xtl ) notes 1. only the oscillator characteristics are shown. see the ac characteristics for instruction execution times. 2. this is the time required for oscillation to stabilize after power (v dd ) is turned on. cautions 1. when the subsystem clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by broken lines to prevent the influence of wiring capacitance, etc. ? the wiring should be kept as short as possible. ? no other signal lines should be crossed. ? keep away from lines carrying a high fluctuating current. ? the oscillator capacitor grounding point should always be at the same potential as v ss . ? do not connect to a ground pattern carrying a high current. ? a signal should not be taken from the oscillator. 2. the subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. xt1 v pp xt2 c4 r1 c3 xt2 xt1
m pd78p058f 34 capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz, unmeasured pins returned to 0 v 15 pf input/output c io f = 1 mhz p01 to p06, p10 to p17, p20 to 15 pf capacitance unmeasured pins returned p27, p30 to p37, p40 to p47, to 0 v p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 p60 to p63 20 pf remark unless specified otherwise, alternate-function pin characteristics are the same as port pin characteristics.
m pd78p058f 35 dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit input voltage, high v ih1 p10 to p17, p21, p23, p30 to p32, p35 to p37, p40 to p47, 0.7 v dd v dd v p50 to p57, p64 to p67, p71, p120 to p127, p130, p131 v ih2 p00 to p06, p20, p22, p24 to p27, p33, p34, p70, p72, 0.8 v dd v dd v reset v ih3 p60 to p63 (n-ch open-drain) 0.7 v dd 15 v v ih4 x1, x2 v dd C 0.5 v dd v v ih5 xt1/p07, xt2 v dd = 4.5 to 6.0 v 0.8 v dd v dd v 0.9 v dd v dd v input voltage, low v il1 p10 to p17, p21, p23, p30 to p32, p35 to p37, p40 to p47, 0 0.3 v dd v p50 to p57, p64 to p67, p71, p120 to p127, p130, p131 v il2 p00 to p06, p20, p22, p24 to p27, p33, p34, p70, p72, 0 0.2 v dd v reset v il3 p60 to p63 v dd = 4.5 to 6.0 v 0 0.3 v dd v 0 0.2 v dd v v il4 x1, x2 0 0.4 v v il5 xt1/p07, xt2 v dd = 4.5 to 6.0 v 0 0.2 v dd v 0 0.1 v dd v output voltage, high v oh v dd = 4.5 to 6.0 v, i oh = C 1 ma v dd C 1.0 v i oh = C100 m av dd C 0.5 v output voltage, low v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 6.0 v, 0.4 2.0 v i ol = 15 ma p01 to p06, p10 to p17, p20 v dd = 4.5 to 6.0 v, 0.4 v to p27, p30 to p37, p40 to i ol = 1.6 ma p47, p64 to p67, p70 to p72, p120 to p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 6.0 v, 0.2 v dd v n-ch open-drain at pull-up time (r = 1 k w ) v ol3 i ol = 400 m a 0.5 v input leakage i lih1 v in = v dd p00 to p06, p10 to p17, p20 3 m a current, high to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p72, p120 to p127, p130, p131, reset i lih2 x1, x2, xt1/p07, xt2 20 m a i lih3 v in = 15 v p60 to p63 80 m a remark unless specified otherwise, alternate-function pin characteristics are the same as port pin characteristics.
m pd78p058f 36 20 500 k w dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit input leakage i lil1 v in = 0 v p00 to p06, p10 to p17, p20 C3 m a current, low to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 C20 m a i lil3 p60 to p63 C3 note m a output leakage i loh v out = v dd 3 m a current, high output leakage i lol v out = 0 v C3 m a current, low software pull-up r v in = 0 v, p01 to p06, p10 v dd = 4.5 to 6.0 v 15 40 90 k w resistor to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 note in p60 to p63, a C200- m a (max.) low-level input leakage current passes only during the 1.5-clock interval (no wait) when the read instruction to port 6 (p6) and port mode register 6 (pm6) is executed. other than the 1.5- clock interval, C3 m a (max.) is passed. remark unless specified otherwise, alternate-function pin characteristics are the same as port pin characteristics.
m pd78p058f 37 v dd = 5.0 v 10% 0.1 30 m a v dd = 3.0 v 10% 0.05 10 m a v dd = 5.0 v 10% 1 30 m a v dd = 3.0 v 10% 0.5 10 m a dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit supply current note 1 i dd1 5.0-mhz crystal oscillation operating v dd = 5.0 v 10% note 5 515ma mode (f xx = 2.5 mhz) note 2 v dd = 3.0 v 10% note 6 0.7 2.1 ma 5.0-mhz crystal oscillation operating v dd = 5.0 v 10% note 5 9.0 27.0 ma mode (f xx = 5.0 mhz) note 3 v dd = 3.0 v 10% note 6 1.0 3.0 ma i dd2 5.0-mhz crystal oscillation halt v dd = 5.0 v 10% 1.4 4.2 ma mode (f xx = 2.5 mhz) note 2 v dd = 3.0 v 10% 0.5 1.5 ma 5.0-mhz crystal oscillation halt v dd = 5.0 v 10% 1.6 4.8 ma mode (f xx = 5.0 mhz) note 3 v dd = 3.0 v 10% 0.65 1.95 ma i dd3 32.768-khz v dd = 5.0 v 10% 135 270 m a crystal oscillation operating mode note 4 v dd = 3.0 v 10% 95 190 m a i dd4 32.768-khz v dd = 5.0 v 10% 25 55 m a crystal oscillation halt mode note 4 v dd = 3.0 v 10% 5 15 m a i dd5 xt1 = v dd stop mode feedback resistor used i dd6 xt1 = v dd stop mode feedback resistor not used notes 1. passed through the v dd and av dd pins. does not include the current which is passed through the a/d converter, d/a converter, and on-chip pull-up resistor. 2. f xx = f x /2 operation (when the oscillation mode selection register (osms) is set to 00h) 3. f xx = f x operation (when osms is set to 01h) 4. when the main system clock is stopped 5. high-speed mode operation (when the processor clock control register (pcc) is set to 00h) 6. low-speed mode operation (when pcc is set to 04h) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency
m pd78p058f 38 ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit cycle time t cy operating on f xx = f x /2 note 1 0.8 64 m s (minimum instruction main system clock f xx = f x note 2 v dd = 4.5 to 6.0 v 0.4 32 m s execution time) 0.8 32 m s operating on subsystem clock 40 122 125 m s ti00 input t tih00 ,v dd = 4.5 to 6.0 v 2/f sam + 0.1 note 3 m s high-/low-level width t til00 2/f sam + 0.2 note 3 m s ti01 input t tih01 ,10 m s high-/low-level width t til01 ti1, ti2 input f ti1 v dd = 4.5 to 6.0 v 0 4 mhz frequency 0 275 khz ti1, ti2 input t tih1 ,v dd = 4.5 to 6.0 v 100 ns high-/low-level width t til1 1.8 m s interrupt input t inth , intp0 v dd = 4.5 to 6.0 v 2/f sam + 0.1 note 3 m s high-/low-level width t intl 2/f sam + 0.2 note 3 m s intp1 to intp6, kr0 to kr7 10 m s reset low-level t rsl 10 m s width notes 1. when oscillation mode selection register (osms) is set to 00h. 2. when osms is set to 01h. 3. f sam can be selected as f xx /2 n , f xx /32, f xx /64, or f xx /128 (n = 0 to 4) by bits 0 and 1 (scs0 and scs1) of the sampling clock selection register (scs). remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency
m pd78p058f 39 t cy vs v dd (main system clock, f xx = f x /2) t cy vs v dd (main system clock, f xx = f x ) 60 10 2.0 1.0 1 023456 0.5 0.4 60 10 2.0 1.0 1 023456 0.5 0.4 supply voltage v dd [v] cycle time t cy [ s] m guaranteed operation range guaranteed operation range supply voltage v dd [v] cycle time t cy [ s] m
m pd78p058f 40 (2) read/write operations (a) when mcs = 1, pcc2 to pcc0 = 000b (t a = C40 to +85 c, v dd = 4.5 to 6.0 v) parameter symbol test conditions min. max. unit astb high-level width t asth 0.85t cy C 50 ns address setup time t ads 0.85t cy C 50 ns address hold time t adh 50 ns data input time from address t add1 (2.85 + 2n)t cy C 80 ns t add2 (4 + 2n)t cy C 100 ns data input time from rd t rdd1 (2 + 2n)t cy C 100 ns t rdd2 (2.85 + 2n)t cy C 100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2 + 2n)t cy C 60 ns t rdl2 (2.85 + 2n)t cy C 60 ns wait input time from rd t rdwt1 0.85t cy C 50 ns t rdwt2 2t cy C 60 ns wait input time from wr t wrwt 2t cy C 60 ns wait low-level width t wtl (1.15 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.85 + 2n)t cy C 100 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (2.85 + 2n)t cy C 60 ns rd delay time from astb t astrd 25 ns wr delay time from astb t astwr 0.85t cy + 20 ns astb - delay time from rd - in external fetch t rdast 0.85t cy C 10 1.15t cy + 20 ns address hold time from rd - in external fetch t rdadh 0.85t cy C 50 1.15t cy + 50 ns write data output time from rd - t rdwd 40 ns write data output time from wr t wrwd 050ns address hold time from wr - t wradh 0.85t cy 1.15t cy + 40 ns rd - delay time from wait - t wtrd 1.15t cy + 40 3.15t cy + 40 ns wr - delay time from wait - t wtwr 1.15t cy + 30 3.15t cy + 30 ns remarks 1. mcs: bit 0 of the oscillation mode selection register (osms) 2. pcc2 to pcc0: bit 2 to bit 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits.
m pd78p058f 41 (b) except when mcs = 1, pcc2 to pcc0 = 000b (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. max. unit astb high-level width t asth t cy C 80 ns address setup time t ads t cy C 80 ns address hold time t adh 0.4t cy C 10 ns data input time from address t add1 (3 + 2n)t cy C 160 ns t add2 (4 + 2n)t cy C 200 ns data input time from rd t rdd1 (1.4 + 2n)t cy C 70 ns t rdd2 (2.4 + 2n)t cy C 70 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.4 + 2n)t cy C 20 ns t rdl2 (2.4 + 2n)t cy C 20 ns wait input time from rd t rdwt1 t cy C 100 ns t rdwt2 2t cy C 100 ns wait input time from wr t wrwt 2t cy C 100 ns wait low-level width t wtl (1 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.4 + 2n)t cy C 60 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (2.4 + 2n)t cy C 20 ns rd delay time from astb t astrd 0.4t cy C 30 ns wr delay time from astb t astwr 1.4t cy C 30 ns astb - delay time from rd - in external fetch t rdast t cy C 10 t cy + 20 ns address hold time from rd - in external fetch t rdadh t cy C 50 t cy + 50 ns write data output time from rd - t rdwd 0.4t cy C 20 ns write data output time from wr t wrwd 060ns address hold time from wr - t wradh t cy t cy + 60 ns rd - delay time from wait - t wtrd 0.6t cy + 180 2.6t cy + 180 ns wr - delay time from wait - t wtwr 0.6t cy + 120 2.6t cy + 120 ns remarks 1. mcs: bit 0 of the oscillation mode selection register (osms) 2. pcc2 to pcc0: bit 2 to bit 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits.
m pd78p058f 42 (3) serial interface (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy1 v dd = 4.5 to 6.0 v 800 ns 1600 ns sck0 high-/low-level width t kh1 ,v dd = 4.5 to 6.0 v t kcy1 /2 C 50 ns t kl1 t kcy1 /2 C 100 ns si0 setup time (to sck0 - )t sik1 v dd = 4.5 to 6.0 v 100 ns 150 ns si0 hold time (from sck0 - )t ksi1 400 ns so0 output delay time from sck0 t kso1 c = 100 pf note 300 ns note c is the sck0 and so0 output line load capacitance. (ii) 3-wire serial i/o mode (sck0 ... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy2 v dd = 4.5 to 6.0 v 800 ns 1600 ns sck0 high-/low-level width t kh2 ,v dd = 4.5 to 6.0 v 400 ns t kl2 800 ns si0 setup time (to sck0 - )t sik2 100 ns si0 hold time (from sck0 - )t ksi2 400 ns so0 output delay time from sck0 t kso2 c = 100 pf note 300 ns sck0 rise, fall time t r2 , when using external 160 ns t f2 device expansion function when not using external 1000 ns device expansion function note c is the so0 output line load capacitance.
m pd78p058f 43 (iii) sbi mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy3 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck0 high-/low-level width t kh3 ,v dd = 4.5 to 6.0 v t kcy3 /2 C 50 ns t kl3 t kcy3 /2 C 150 ns sb0, sb1 setup time (to sck0 - )t sik3 v dd = 4.5 to 6.0 v 100 ns 300 ns sb0, sb1 hold time (from sck0 - )t ksi3 t kcy3 /2 ns sb0, sb1 output delay time from t kso3 r = 1 k w, v dd = 4.5 to 6.0 v 0 250 ns sck0 c = 100 pf note 0 1000 ns sb0, sb1 from sck0 - t ksb t kcy3 ns sck0 from sb0, sb1 t sbk t kcy3 ns sb0, sb1 high-level width t sbh t kcy3 ns sb0, sb1 low-level width t sbl t kcy3 ns note r and c are the sck0, sb0, and sb1 output line load resistance and load capacitance. (iv) sbi mode (sck0 ... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy4 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck0 high-/low-level width t kh4 ,v dd = 4.5 to 6.0 v 400 ns t kl4 1600 ns sb0, sb1 setup time (to sck0 - )t sik4 v dd = 4.5 to 6.0 v 100 ns 300 ns sb0, sb1 hold time (from sck0 - )t ksi4 t kcy4 /2 ns sb0, sb1 output delay time from t kso4 r = 1 k w, v dd = 4.5 to 6.0 v 0 300 ns sck0 c = 100 pf note 0 1000 ns sb0, sb1 from sck0 - t ksb t kcy4 ns sck0 from sb0, sb1 t sbk t kcy4 ns sb0, sb1 high-level width t sbh t kcy4 ns sb0, sb1 low-level width t sbl t kcy4 ns sck0 rise, fall time t r4 , when using external device 160 ns t f4 expansion function when not using external 1000 ns device expansion function note r and c are the sb0 and sb1 output line load resistance and load capacitance.
m pd78p058f 44 (v) 2-wire serial i/o mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy5 r = 1 k w, 1600 ns sck0 high-level width t kh5 c = 100 pf note t kcy5 /2 C 160 ns sck0 low-level width t kl5 v dd = 4.5 to 6.0 v t kcy5 /2 C 50 ns t kcy5 /2 C 100 ns sb0, sb1 setup time (to sck0 - )t sik5 v dd = 4.5 to 6.0 v 300 ns 350 ns sb0, sb1 hold time (from sck0 - )t ksi5 600 ns sb0, sb1 output delay time t kso5 0 300 ns from sck0 note r and c are the sck0, sb0, and sb1 output line load resistance and load capacitance. (vi) 2-wire serial i/o mode (sck0 ... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy6 1600 ns sck0 high-level width t kh6 650 ns sck0 low-level width t kl6 800 ns sb0, sb1 setup time (to sck0 - )t sik6 100 ns sb0, sb1 hold time (from sck0 - )t ksi6 t kcy6 /2 ns sb0, sb1 output delay time t kso6 r = 1 k w, v dd = 4.5 to 6.0 v 0 300 ns from sck0 c = 100 pf note 0 500 ns sck0 rise, fall time t r6 , when using external device 160 ns t f6 expansion function when not using external 1000 ns device expansion function note r and c are the sb0 and sb1 output line load resistance and load capacitance.
m pd78p058f 45 (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy7 v dd = 4.5 to 6.0 v 800 ns 1600 ns sck1 high-/low-level width t kh7 ,v dd = 4.5 to 6.0 v t kcy7 /2 C 50 ns t kl7 t kcy7 /2 C 100 ns si1 setup time (to sck1 - )t sik7 v dd = 4.5 to 6.0 v 100 ns 150 ns si1 hold time (from sck1 - )t ksi7 400 ns so1 output delay time from sck1 t kso7 c = 100 pf note 300 ns note c is the sck1 and so1 output line load capacitance. (ii) 3-wire serial i/o mode (sck1 ... external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy8 v dd = 4.5 to 6.0 v 800 ns 1600 ns sck1 high-/low-level width t kh8 ,v dd = 4.5 to 6.0 v 400 ns t kl8 800 ns si1 setup time (to sck1 - )t sik8 100 ns si1 hold time (from sck1 - )t ksi8 400 ns so1 output delay time from sck1 t kso8 c = 100 pf note 300 ns sck1 rise, fall time t r8 , when using external device 160 ns t f8 expansion function when not using external 1000 ns device expansion function note c is the so1 output line load capacitance.
m pd78p058f 46 (iii) automatic transmission/reception function 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy9 v dd = 4.5 to 6.0 v 800 ns 1600 ns sck1 high-/low-level width t kh9 ,v dd = 4.5 to 6.0 v t kcy9 /2 C 50 ns t kl9 t kcy9 /2 C 100 ns si1 setup time (to sck1 - )t sik9 v dd = 4.5 to 6.0 v 100 ns 150 ns si1 hold time (from sck1 - )t ksi9 400 ns so1 output delay time from sck1 t kso9 c = 100 pf note 300 ns stb - from sck1 - t sbd t kcy9 /2 C 100 t kcy9 /2 + 100 ns strobe signal high-level width t sbw t kcy9 C 30 t kcy9 + 30 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh v dd = 4.5 to 6.0 v 100 ns (from busy signal detection timing) 150 ns sck1 from busy inactive t sps 2t kcy9 ns note c is the sck1 and so1 output line load capacitance. (iv) automatic transmission/reception function 3-wire serial i/o mode (sck1 ... external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy10 v dd = 4.5 to 6.0 v 800 ns 1600 ns sck1 high-/low-level width t kh10 ,v dd = 4.5 to 6.0 v 400 ns t kl10 800 ns si1 setup time (to sck1 - )t sik10 100 ns si1 hold time (from sck1 - )t ksi10 400 ns so1 output delay time from sck1 t kso10 c = 100 pf note 300 ns sck1 rise, fall time t r10 , when using external device 160 ns t f10 expansion function when not using external 1000 ns device expansion function note c is the so1 output line load capacitance.
m pd78p058f 47 (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy11 v dd = 4.5 to 6.0 v 800 ns 1600 ns sck2 high-/low-level width t kh11 ,v dd = 4.5 to 6.0 v t kcy11 /2 C 50 ns t kl11 t kcy11 /2 C 100 ns si2 setup time (to sck2 - )t sik11 v dd = 4.5 to 6.0 v 100 ns 150 ns si2 hold time (from sck2 - )t ksi11 400 ns so2 output delay time from sck2 t kso11 c = 100 pf note 300 ns note c is the sck2 and so2 output line load capacitance. (ii) uart mode (dedicated baud rate generator output) parameter symbol test conditions min. typ. max. unit transfer rate v dd = 4.5 to 6.0 v 78125 bps 39063 bps (iii) uart mode (external clock input) parameter symbol test conditions min. typ. max. unit asck cycle time t kcy12 v dd = 4.5 to 6.0 v 800 ns 1600 ns asck high-/low-level t kh12 ,v dd = 4.5 to 6.0 v 400 ns width t kl12 800 ns transfer rate v dd = 4.5 to 6.0 v 39063 bps 19531 bps asck rise, fall time t r12 ,v dd = 4.5 to 6.0 v, 1000 ns t f12 when not using external device expansion function 160 ns
m pd78p058f 48 ac timing test point (excluding x1, xt1 inputs) clock timing ti timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points x1 input 1/f x t xl t xh v dd ?0.5 v 0.4 v xt1 input 1/f xt t xtl t xth v ih5 (min.) v il5 (max.) ti00, ti01 t til00 , t til01 t tih00 , t tih01 ti1, ti2 1/f ti1 t til1 t tih1
m pd78p058f 49 read/write operations external fetch (no wait): external fetch (wait insertion): t asth t adh t add1 hi-z t ads a8 to a15 ad0 to ad7 astb rd t rdh high-order 8-bit address operation code low-order 8-bit address t rdd1 t rdadh t rdast t rdl1 t astrd t asth t add1 hi-z t ads t rdl1 a8 to a15 ad0 to ad7 astb rd wait t rdh high-order 8-bit address operation code low-order 8-bit address t rdd1 t rdwt1 t adh t rdadh t rdast t wtl t astrd t wtrd
m pd78p058f 50 external data access (no wait): external data access (wait insertion): a8 to a15 ad0 to ad7 rd wr astb t wrl1 t astwr t wrwd t rdwd t wdh t wds t rdl2 t asth t ads t rdd2 t rdh t astrd t add2 high-order 8-bit address hi-z t adh read data write data hi-z hi-z low-order 8-bit address t wradh a8 to a15 ad0 to ad7 rd wait t rdwt2 t wrwt t wtwr t wtl t wrwd t rdwd t wdh t astrd t asth t ads t adh t rdh wr astb high-order 8-bit address read data write data hi-z hi-z hi-z t add2 t rdd2 t wtl t wtrd t wds t wradh t wrl1 t rdl2 low-order 8-bit address t astwr
m pd78p058f 51 serial transfer timing 3-wire serial i/o mode: remark m = 1, 2, 7, 8, 11 n = 2, 8 sbi mode (bus release signal transfer): sbi mode (command signal transfer): t sik3, 4 t kcy3, 4 sck0 t ksb t sbk t ksi3, 4 t kso3, 4 sb0, sb1 t kh3, 4 t kl3, 4 t r4 t f4 t kcym t khm sck0 to sck2 si0 to si2 so0 to so2 t ksom input data output data t rn t fn t ksim t sikm t klm t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t sbl t sbh t ksb t sbk t ksi3, 4 t kso3, 4 sb0, sb1 t r4 t f4
m pd78p058f 52 2-wire serial i/o mode: automatic transmission/reception function 3-wire serial i/o mode: t kso5, 6 t sik5, 6 t kcy5, 6 t kl5, 6 t kh5, 6 sck0 t ksi5, 6 sb0, sb1 t r6 t f6 note the signal is not actually low here, but is represented this way to show the timing. t bys sck1 t sps busy ( active hi g h ) 789 note 10 note 1 t byh 10+n note automatic transmission/reception function 3-wire serial i/o mode (busy processing): t sbw t sbd t kcy9, 10 t kl9, 10 t kh9, 10 t f10 t ksi9, 10 t kso9, 10 t sik9, 10 t r10 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb
m pd78p058f 53 uart mode (external clock input): t kl12 asck t kh12 t kcy12 t r12 t f12
m pd78p058f 54 a/d converter characteristics (t a = C40 to +85 c, av dd = v dd = 2.7 to 6.0 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit total error note 2.7 v av ref0 av dd 1.4 % conversion time t conv 19.1 200 m s sampling time t samp 12/f xx m s analog input voltage v ian av ss av ref0 v reference voltage av ref0 2.7 av dd v av ref0 to av ss resistance r airef0 414 k w note excluding quantization error ( 1/2lsb). shown as a percentage of the full scale value. caution for pins which also function as port pins (see 2.1 pins in normal operating mode (1) port pins), do not perform the following operations during a/d conversion. if these operations are performed, the total error ratings cannot be kept. <1> rewrite the output latch while the pin is used as a port pin. <2> change the output level of the pin used as an output pin, even if it is not used as a port pin. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency d/a converter characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit resolution 8 bit total error r = 2 m w note 1 1.2 % r = 4 m w note 1 0.8 % r = 10 m w note 1 0.6 % settling time c = 30 pf note 1 4.5 v av ref1 6.0 v 10 m s 2.7 v av ref1 < 4.5 v 15 m s output resistance r o note 2 10 k w analog reference av ref1 2.0 v dd v voltage av ref1 to av ss resistance r airef1 dacs0, dacs1 = 55h note 2 48 k w notes 1. r and c are the d/a converter output pin load resistance and load capacitance. 2. value for one d/a converter channel remark dacs0, dacs1 : d/a conversion value setting register 0, 1
m pd78p058f 55 data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) parameter symbol test conditions min. typ. max. unit data retention v dddr 1.8 6.0 v supply voltage data retention i dddr v dddr = 1.8 v 0.1 10 m a supply current subsystem clock stopped, feedback resistor disconnected release signal setup t srel 0 m s time oscillation t wait stabilization wait time note 2 12 /f xx , or 2 14 /f xx through 2 17 /f xx can be selected by bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time selection register (osts). remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode release by reset) release by reset 2 17 /f x ms release by interrupt note ms data retention timing (standby release signal: stop mode release by interrupt signal) t srel t wait v dd reset stop mode data retention mode internal reset operation halt mode operating mode v dddr stop instruction execution t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
m pd78p058f 56 interrupt input timing reset input timing t rsl reset t intl t inth intp0 to intp6
m pd78p058f 57 prom programming characteristics dc characteristics (1) prom write mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) parameter symbol symbol note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7 v dd v dd v input voltage, low v il v il 0 0.3 v dd v output voltage, high v oh v oh i oh = C1 ma v dd C 1.0 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd C10 +10 m a v pp supply voltage v pp v pp 12.2 12.5 12.8 v v dd supply voltage v dd v cc 6.25 6.5 6.75 v v pp supply current i pp i pp pgm = v il 50 ma v dd supply current i dd i cc 50 ma (2) prom read mode (t a = 25 5 c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol symbol note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7 v dd v dd v input voltage, low v il v il 0 0.3 v dd v output voltage, high v oh1 v oh1 i oh = C1 ma v dd C 1.0 v v oh2 v oh2 i oh = C100 m av dd C 0.5 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd C10 +10 m a output leakage current i lo i lo 0 v out v dd , oe = v ih C10 +10 m a v pp supply voltage v pp v pp v dd C 0.6 v dd v dd + 0.6 v v dd supply voltage v dd v cc 4.5 5.0 5.5 v v pp supply current i pp i pp v pp = v dd 100 m a v dd supply current i dd i cca1 ce = v il , v in = v ih 50 ma note corresponding symbols for the m pd27c1001a.
m pd78p058f 58 ac characteristics (1) prom write mode (a) page program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) parameter symbol symbol note test conditions min. typ. max. unit address setup time (to oe )t as t as 2 m s oe setting time t oes t oes 2 m s ce setup time (to oe )t ces t ces 2 m s input data setup time (to oe )t ds t ds 2 m s address hold time (from oe - )t ah t ah 2 m s t ahl t ahl 2 m s t ahv t ahv 0 m s input data hold time (from oe - )t dh t dh 2 m s data output float delay time from oe - t df t df 0 250 ns v pp setup time (to oe )t vps t vps 1.0 ms v dd setup time (to oe )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms valid data delay time from oe t oe t oe 1 m s oe pulse width during data latching t lw t lw 1 m s pgm setting time t pgms t pgms 2 m s ce hold time t ceh t ceh 2 m s oe hold time t oeh t oeh 2 m s (b) byte program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) parameter symbol symbol note test conditions min. typ. max. unit address setup time (to pgm )t as t as 2 m s oe setting time t oes t oes 2 m s ce setup time (to pgm )t ces t ces 2 m s input data setup time (to pgm )t ds t ds 2 m s address hold time (from oe - )t ah t ah 2 m s input data hold time (from pgm - )t dh t dh 2 m s data output float delay time from oe - t df t df 0 250 ns v pp setup time (to pgm )t vps t vps 1.0 ms v dd setup time (to pgm )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms valid data delay time from oe t oe t oe 1 m s oe hold time t oeh 2 m s note corresponding symbols for the m pd27c1001a.
m pd78p058f 59 (2) prom read mode (t a = 25 5 c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol symbol note test conditions min. typ. max. unit data output delay time from address t acc t acc ce = oe = v il 800 ns data output delay time from ce t ce t ce oe = v il 800 ns data output delay time from oe t oe t oe ce = v il 200 ns data output float delay time from oe - t df t df ce = v il 060ns data hold time from address t oh t oh ce = oe = v il 0ns note corresponding symbols for the m pd27c1001a. (3) prom programming mode setting (t a = 25 c, v ss = 0 v) parameter symbol test conditions min. typ. max. unit prom programming mode setup time t sma 10 m s
m pd78p058f 60 prom write mode timing (page program mode) a2 to a16 a0, a1 d0 to d7 v pp v pp v dd v dd v dd +1.5 v dd ce v ih v il pgm v ih v il oe v ih v il page data latch page program program verify data output data input t as t ds t vps t vds t lw t dh t pgms t ceh t pw t oes t oeh t ah t ahl hi-z hi-z hi-z t oe t df t ahv t ces
m pd78p058f 61 prom write mode timing (byte program mode) cautions 1. v dd should be applied before v pp , and removed after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. reliability may be adversely affected if removal/reinsertion is performed while +12.5 v is being applied to v pp . prom read mode timing notes 1. if you want to read within the t acc range, make the oe input delay time from the fall of ce a maximum of t acc C t oe . 2. t df is the time from when either oe or ce first reaches v ih . a0 to a16 d0 to d7 ce v ih v il v ih v il oe t ce t oh t df t acc hi-z hi-z effective address note 1 note 2 note 1 data output t oe a0 to a16 d0 to d7 v pp v pp v dd v dd v dd +1.5 v dd ce pgm v ih v ih v ih v il v il v il oe page data latch program program verify t as t ds t dh t vds t ces t pw t oes t vps hi-z hi-z hi-z t oeh t df t ah t oe data input data output
m pd78p058f 62 prom programming mode setting timing t sma a0 to a16 0 v dd 0 v dd v dd v pp reset effective address
m pd78p058f 63 8. package drawings package drawing of m pd78p058fgc-3b9 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. l 0.8 0.2 0.031 +0.009 ?.008 m 0.15 0.006 n 0.10 0.004 p 2.7 0.106 a 17.2 0.4 0.677 0.016 b 14.0 0.2 0.551 +0.009 ?.008 c 14.0 0.2 0.551 +0.009 ?.008 d 17.2 0.4 0.677 0.016 f 0.825 0.032 g 0.825 0.032 h 0.30 0.10 0.012 +0.004 ?.005 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) q 0.1 0.1 0.004 0.004 r5 5 5 5 +0.10 ?.05 +0.004 ?.003 m m l k j h q p n r detail of lead end i g k 1.6 0.2 0.063 0.008 60 61 40 80 1 21 20 41 a b cd f s s80gc-65-3b9-4 s 3.0 max. 0.119 max. remark the dimensions and materials of es product are the same as those of mass-production products.
m pd78p058f 64 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. p80gc-65-8bt f 0.825 0.032 b 14.00 0.20 0.551 +0.009 ?.008 s 1.70 max. 0.067 max. m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 +0.009 ?.008 c 14.00 0.20 0.551 +0.009 ?.008 a 17.20 0.20 0.677 0.008 g 0.825 0.032 h 0.32 0.06 0.013 +0.002 ?.003 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) k 1.60 0.20 0.063 0.008 l 0.80 0.20 0.031 +0.009 ?.008 n 0.10 0.004 p 1.40 0.10 0.055 0.004 q 0.125 0.075 0.005 0.003 r3 3 +7 ? +7 ? d 17.20 0.20 0.677 0.008 41 60 40 61 21 80 20 1 m s q r k m l a b c d j h i f g p n detail of lead end package drawing of m pd78p058fgc-8bt
m pd78p058f 65 9. recommended soldering conditions the m pd78p058f should be soldered and mounted under the conditions recommended below. for details of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, please contact your nec sales represen- tative. table 9-1. surface mount type soldering conditions (1/2) (1) m pd78p058fgc-3b9 : 80-pin plastic qfp (14 14 mm, resin thickness: 2.7 mm) soldering method soldering conditions symbol infrared reflow ir35-207-3 vps vp15-207-3 wave soldering ws60-207-1 pin partial heating note the number of days for storage after the dry pack has been opened. storage conditions are 25 c and 65% rh max. caution use of more than one soldering method should be avoided (except the pin partial heating method). package peak temperature: 235 c, reflow time: 30 seconds or below (210 c or higher), number of reflow processes: 3 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 20 hours) package peak temperature: 215 c, reflow time: 40 seconds or below (200 c or higher), number of reflow processes: 3 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 20 hours) solder temperature: 260 c or below, flow time: 10 seconds or below, number of flow processes: 1, preheating temperature: 120 c or below (package surface tempera- ture), exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 20 hours) pin temperature: 300 c or below, time: 3 seconds or below (per side of device)
m pd78p058f 66 table 9-1. surface mount type soldering conditions (2/2) (2) m pd78p058fgc-8bt : 80-pin plastic qfp (14 14 mm, resin thickness: 1.4 mm) soldering method soldering conditions symbol infrared reflow ir35-107-2 vps vp15-107-2 wave soldering ws60-107-1 pin partial heating note the number of days for storage after the dry pack has been opened. storage conditions are 25 c and 65% rh max. caution use of more than one soldering method should be avoided (except the pin partial heating method). package peak temperature: 235 c, reflow time: 30 seconds or below (210 c or higher), number of reflow processes: 2 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours) package peak temperature: 215 c, reflow time: 40 seconds or below (200 c or higher), number of reflow processes: 2 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours) solder temperature: 260 c or below, flow time: 10 seconds or below, number of flow processes: 1, preheating temperature: 120 c or below (package surface tempera- ture), exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours) pin temperature: 300 c or below, time: 3 seconds or below (per side of device)
m pd78p058f 67 appendix a. development tools the following support tools are available for system development using the m pd78p058f. language processing software ra78k/0 notes 1, 2, 3, 4 78k/0 series common assembler package cc78k/0 notes 1, 2, 3, 4 78k/0 series common c compiler package df78054 notes 1, 2, 3, 4 m pd78054 subseries common device file cc78k/0-l notes 1, 2, 3, 4 78k/0 series common c compiler library source file prom writing tools pg-1500 prom programmer pa-78p054gc programmer adapter connected to a pg-1500 pg-1500 controller notes 1, 2 pg-1500 control program debugging tools ie-78000-r 78k/0 series common in-circuit emulator ie-78000-r-a 78k/0 series common in-circuit emulator (for integrated debugger) ie-78000-r-bk 78k/0 series common break board ie-78064-r-em note 8 emulation board common to m pd78064 subseries ie-780308-r-em emulation board common to m pd780308 subseries ie-78000-r-sv3 interface adapter and cable (for ie-78000-r-a) when using ews as a host machine ie-70000-98-if-b interface adapter (for ie-78000-r-a) when using pc-9800 series (except notebook type computer) as a host machine ie-70000-98n-if interface adapter and cable (for ie-78000-r-a) when using pc-9800 series notebook type computer as a host machine ie-70000-pc-if-b interface adapter (for ie-78000-r-a) when using ibm pc/at? and its compatibles as a host machine ep-78230gc-r emulation probe common to m pd78234 subseries ev-9200gc-80 socket for mounting on target system board created for 80-pin plastic qfp (see figure a-1 ) (gc-3b9, gc-8bt type) sm78k0 notes 5, 6, 7 78k/0 series common system simulator id78k0 notes 4, 5, 6, 7 integrated debugger for ie-78000-r-a sd78k/0 notes 1, 2 screen debugger for ie-78000-r df78054 notes 1, 2, 4, 5, 6, 7 device file common to m pd78054 subseries
m pd78p058f 68 real-time os rx78k/0 notes 1, 2, 3, 4 78k/0 series real-time os mx78k0 notes 1, 2, 3, 4 78k/0 series os fuzzy inference development support system fe9000 note 1 /fe9200 note 6 fuzzy knowledge data input tool ft9080 note 1 /ft9085 note 2 translator fi78k0 notes 1, 2 fuzzy inference module fd78k0 notes 1, 2 fuzzy inference debugger notes 1. pc-9800 series (ms-dos tm ) based 2. ibm pc/at and its compatibles (pc dos tm /ibm dos tm /ms-dos) based 3. hp9000 series 300 tm (hp-ux tm ) based 4. hp9000 series 700 tm (hp-ux) based, sparcstation tm (sunos tm ) based, ews4800 series (ews-ux/v) based 5. pc-9800 series (ms-dos + windows tm ) based 6. ibm pc/at and its compatibles (pc dos/ibm dos/ms-dos + windows) based 7. news tm (news-os tm ) based 8. maintenance product remarks 1. for third party development tools, see 78k/0 series selection guide (u11126e) . 2. the ra78k/0, cc78k/0, sm78k0, id78k0, sd78k/0, and rx78k/0 are used in combination with the df78054.
m pd78p058f 69 drawing of conversion socket (ev-9200gc-80) and recommended footprint figure a-1. drawing of ev-9200gc-80 (for reference only) a f d 1 no.1 pin index e ev-9200gc-80 b c m n o l k s r q p i h j g ev-9200gc-80-g1e item millimeters inches a b c d e f g h i j k l m n o p q r s 18.0 14.4 14.4 18.0 4-c 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.709 0.567 0.567 0.709 4-c 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059 f f f f
m pd78p058f 70 figure a-2. recommended footprint of ev-9200gc-80 (for reference only) a f d e c b g j k l h i 0.026 0.748=0.486 0.026 0.748=0.486 ev-9200gc-80-p1e item millimeters inches a b c d e f g h i j k l 19.7 15.0 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 0.776 0.591 0.591 0.776 0.236 0.236 0.014 0.093 0.091 0.062 0.65 0.02 19=12.35 0.05 0.65 0.02 19=12.35 0.05 f f +0.001 e0.002 +0.003 e0.002 +0.001 e0.002 +0.003 e0.002 +0.003 e0.002 +0.003 e0.002 +0.001 e0.001 +0.001 e0.002 f +0.001 e0.002 f f dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution f
m pd78p058f 71 appendix b. related documents device documents document name document no. document no. (english) (japanese) m pd78058f, 78058fy subseries users manual u12068e u12068j m pd78p058f data sheet this document u11796j m pd78056f, 78058f data sheet u11795e u11795j 78k/0 series users manual instructions u12326e u12326j 78k/0 series instruction set u10904j 78k/0 series instruction table u10903j caution the contents of the above documents are subject to change without notice. please ensure that the latest versions are used in design work, etc.
m pd78p058f 72 development tool documents (user's manual) document name document no. document no. (english) (japanese) ra78k series assembler package operation eeu-1399 eeu-809 language eeu-1404 eeu-815 ra78k series structured assembler preprocessor eeu-1402 u12323j ra78k0 assembler package operation u11802e u11802j assembly language u11801e u11801j structured assembly language u11789e u11789j cc78k series c compiler operation eeu-1280 eeu-656 language eeu-1284 eeu-655 cc78k0 c compiler operation u11517e u11517j language u11518e u11518j cc78k/0 c compiler application note programming know-how eea-1208 eea-618 cc78k series library source file u12322j pg-1500 prom programmer eeu-1335 u11940j pg-1500 controller pc-9800 series (ms-dos) based eeu-1291 eeu-704 pg-1500 controller ibm pc series (pc dos) based u10540e eeu-5008 ie-78000-r u11376e u11376j ie-78000-r-a u10057e u10057j ie-78000-r-bk eeu-1427 eeu-867 ie-78064-r-em eeu-1443 eeu-905 ie-780308-r-em u11362e u11362j ep-78230 eeu-1515 eeu-985 sm78k0 system simulator windows based reference u10181e u10181j sm78k series system simulator external part user open u10092e u10092j interface specifications id78k0 integrated debugger ews based reference u11151j id78k0 integrated debugger pc based reference u11539e u11539j id78k0 integrated debugger windows based guide u11649e u11649j sd78k/0 screen debugger introduction eeu-852 pc-9800 series (ms-dos) based reference u10952j sd78k/0 screen debugger introduction u10539e eeu-5024 ibm pc/at (pc dos) based reference u11279e u11279j caution the contents of the above documents are subject to change without notice. please ensure that the latest versions are used in design work, etc.
m pd78p058f 73 embedded software documents (user's manual) document name document no. document no. (english) (japanese) 78k/0 series real-time os basics u11537e u11537j installation u11536e u11536j 78k/0 series os mx78k0 basics u12257e u12257j fuzzy knowledge data input tools eeu-1438 eeu-829 78k/0, 78k/ii, 87ad series eeu-1444 eeu-862 fuzzy inference development support system translator 78k/0 series fuzzy inference development support system fuzzy inference module eeu-1441 eeu-858 78k/0 series fuzzy inference development support system fuzzy inference debugger eeu-1458 eeu-921 other documents document name document no. document no. (english) (japanese) ic package manual c10943x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j electrostatic discharge (esd) test mem-539 guide to quality assurance for semiconductor devices mei-1202 c11893j microcomputer product series guide u11416j caution the contents of the above documents are subject to change without notice. please ensure that the latest versions are used in design work, etc.
m pd78p058f 74 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd78p058f 75 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd78p058f fip, iebus, and qtop are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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